Program
16490
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Program

Nikil_D_Dutt

Keynote:  Omni-Layer Intelligence Requires Cross-Layer Self-Awareness

Speaker: Nikil Dutt, Distinguished Professor of CS, EECS & Cognitive Sciences, UC Irvine, USA

 

Talk Summary: The principle of layered design abstractions has facilitated the development of myriad applications, ranging from small form-factor IoT devices to complex system-of-systems.  While this clean separation of abstraction levels eases the task of modeling, design, validation and verification, these systems demand a tight coupling of computation, communication and control across the abstraction stack to meet energy, performance, reliability and security needs. Furthermore, the fast-evolving landscape of emerging computing substrates, coupled with highly dynamic operational behaviors operating in varying environmental conditions poses significant challenges to meet the (often conflicting) goals of resiliency, energy, heat, cost, performance, security, etc.  I posit that effective  deployment of intelligence  across the abstraction stack necessarily requires a cross-layer approach, coupled with computational cognitive intelligence (CCI) principles that enable the system to learn and evolve at runtime. A key feature of  the CCI paradigm is  computational self-awareness through introspection (i.e., modeling and observing its own internal and external behaviors) combined with both reflexive and reflective adaptations via cross-layer physical and virtual sensing and actuations applied across multiple layers of the system abstraction stack. In this context, omni-layer intelligence requires a fundamental change from  classical layered computing to a cross-layer CCI paradigm that embodies self-awareness principles. In the past decade we have applied these concepts across multiple projects spanning nanoscale computing, healthcare IoT, data center memory, and end-to-end computational pipelines for autonomous systems.  The rise of generative AI, coupled with distributed autonomy poses new challenges for detecting and managing emergent behaviors to ensure system safety.  I will close with some thoughts on how CCI principles and cross-layer self-awareness might be applied to address these challenges.

 

 

 

Biography: Nikil D. Dutt is a Chancellor’s Professor at the University of California, Irvine, with academic appointments in the CS, EECS, and Cognitive Sciences departments.  He received a B.E.(Hons) in Mechanical Engineering from the Birla Institute of Technology and Science, Pilani, India in 1980, an M.S. in Computer Science from the Pennsylvania State University in 1983, and a Ph.D. in Computer Science from the University of Illinois at Urbana-Champaign in 1989. He is affiliated with the following Centers at UCI: Center for Embedded Computer Systems (CECS), Center for Cognitive Neuroscience and Engineering (CENCE), California Institute for Telecommunications and Information Technology (Calit2), the Center for Pervasive Communications and Computing (CPCC), and the Laboratory for Ubiquitous Computing and Interaction (LUCI). Professor Dutt’s research interests are in embedded systems, electronic design automation, computer architecture, optimizing compilers, system specification techniques, distributed systems, formal methods, and brain-inspired architectures and computing. He is a coauthor of seven books: “High-Level Synthesis: Introduction to Chip and System Design”, Kluwer Academic Publishers, 1992, “Memory Issues in Embedded Systems-on-Chip: Optimizations and Exploration”, Kluwer Academic Publishers, 1999, “Memory Architecture Exploration for Programmable Embedded Systems”, Kluwer Academic Publishers, 2003, “SPARK: A Parallelizing Approach to the High-Level Synthesis of Digital Circuits”, Kluwer Academic Publishers, 2004, “Functional Validation of Programmable Embedded Architectures: A Top-Down Approach”, Springer-Verlag, 2005, “On-chip Communication Architectures: Current Practice, Research and Future Trends,” Morgan Kaufman/Elsevier Systems-on-Silicon Series, 2008, and “Processor Description Languages: Applications and Methodologies,” Morgan Kaufman/Elsevier Systems-on-Silicon Series, 2008. Professor Dutt’s research has been recognized by Best Paper Awards at the following conferences: CHDL’89, CHDL’91, VLSI Design 2003, CODES+ISSS 2003, CNCC 2006, ASPDAC 2006, IJCNN 2009, and DATE 2012; and Best Paper Award Nominations at: WASP 2004, DAC 2005, VLSI Design 2006, and CASES 2011.  He has also received a number of departmental and campus awards for excellence in teaching at UC Irvine. Professor Dutt currently serves as Associate Editor of ACM Transactions on Embedded Computer Systems (TECS) and of IEEE Transactions on VLSI Systems (TVLSI). He served as Editor-in-Chief of ACM Transactions on Design Automation of Electronic Systems (TODAES) between 2004-2008. He was an ACM SIGDA Distinguished Lecturer during 2001-2002, and an IEEE Computer Society Distinguished Visitor for 2003-2005.  He has served on the steering, organizing, and program committees of several premier CAD and Embedded System conferences and workshops.  His recent major conference activity includes: ESWeek Steering Committee Chair and TPC Co-Chair DAC-2010/2011. He currently serves on, or has served on the ACM Publications Board, the advisory boards of ACM SIGBED, ACM SIGDA, and IFIP WG 10.5. He is a Fellow of the IEEE, an ACM Distinguished Scientist, and an IFIP Silver Core awardee.

 

 

 

McCann-Julie-Photo

Keynote: Finding Rubies in the Dust

Speaker: Professor Julie A. McCann, Department of Computing, Imperial College London, UK

 

Talk Summary: Since the early days of Wireless Sensor Networks to today’s Internet of Things there have been over twenty five years of research. A quick Google Scholar search reveals well over 700k papers with ‘Wireless Sensor Network’ and  500k with ‘Internet of Things’. However, when one talks to real users in the worlds of civil engineering, environment modelling, digital agriculture and the industrial IoT etc. they complain about the systems still being flaky and completely unusable after a few years. Real users of networked sensor systems want smart infrastructures that are reliable. In my talk I will discuss some of the issues sensor systems designers face, and put forward some of my thoughts of how we can reuse our infrastructure and our knowledge of cyber-physical interaction so we can turn noise into new or better signals.

 

 

Biography: Prof. McCann heads up Adaptive Emergent Systems Engineering (AESE) in the Dept of Computing where she works with a highly multi-disciplinary group of Post Docs and PhD students from a broad spectra of backgrounds. She leads the Resilient and Robust Infrastructure challenge part of the Data Centric Engineering theme in the Alan Turing Institute, she is PI for the  NRF funded Singapore Eco Cities initiative, and is Deputy Director of PeTraS and therein leads the Logistics 4.0 project with the Tate Modern, ARM and Ordinance Survey. She is Imperial PI for the EPSRC Science of Sensing Systems Software (S4) programme grant.  Until recently she was the Co-director of the Intel Collaborative Research Institute on Sustainable Connected Cities, the Co-PI of the NEC Smart Water Lab, and Director of the cross-Imperial Smart Connected Futures Network. She has chaired and remains actively involved with the field’s top conferences (including Infocom, Sensys, IPSN, and EWSN) and is an Associated Editor for IoT-J. She currently delivers the Pervasive Computing teaching module and in the past she lectured Operating Systems courses.  She was chair of the Department of Computing Equality and Diversity committee (2018-2021), is a Fellow of the British Computer Society, a Chartered Engineer and consults on computer-based futures for TV and Film.

Partha Maji

Keynote:  Speeding Up Generative AI

Speaker: Dr Partha Maji, Director of AI Hardware Acceleration, Tenstorrent Inc., Cambridge, UK

 

Talk Summary: This presentation will address the implementation challenges associated with generative AI on emerging spatial computing hardware. We will conduct a comprehensive analysis of several state-of-the-art AI hardware accelerator architectures currently emerging in the industry. Subsequently, we will delve into the architecture of state-of-the-art Large Language Models (LLMs) and investigate diverse strategies aimed at effectively mapping these models onto the underlying hardware infrastructure. Concluding the presentation, we will underscore various challenges and delineate opportunities for further research within the realms of model design and optimization.

 

 

 

Biography: Partha Maji currently holds the role of Technical Director of ML Hardware Acceleration at Tenstorrent, a prominent AI Hardware startup based in the United States. In this capacity, he leads AI research and advanced implementation initiatives aimed at accelerating transformer-based generative inference and training utilizing Tenstorrent’s innovative hardware accelerator. Prior to assuming this role, he led the ML Research team at Arm Cambridge, UK. Boasting over 18 years of industry experience, Partha led numerous successful projects spanning various domains at the intersection of AI/ML algorithms, software/compilers, hardware architectures and chip design. Partha’s noteworthy contributions have earned him several excellence awards, including the Mentor Graphics Prize for outstanding achievement. His research on on-chip interconnect has been acclaimed, garnering awards from Epson Europe and the IET in the UK. Additionally, the European Neural Network Society has acknowledged his significant contributions to machine learning research. Partha has served as a distinguished speaker and industry panelist at major machine learning events and conferences, including NeurIPS, ICML, FPL, AICAS, and the Embedded Vision Summit. He holds over 30 patents in the areas of AI and hardware architecture. Partha earned his PhD in Computer Science from the University of Cambridge.